Electronics & Circuits · Study deck

DAC and PWM: Actuator Selection and Validation

An LED or motor is an actuator, a device that acts on its surroundings; an audio input is a different kind of load.

Voltage Vera is your guide for this deck.

analogdigitaloutput

Voltage Vera, the module guide, in a scene from this chapter.

After studying this chapter

Learning objectives

You will be able to:

Explain: That observation connects duty-cycle arithmetic to the selection rule: PWM suits tolerant loads, while quiet bias and measurement signals need filtering or a true DAC.
Explain: An LED or motor is an actuator, a device that acts on its surroundings; an audio input is a different kind of load.
Explain: This page turns those ideas into a design contract: what the load actually sees, what timer settings cost, and what error matters most.
Explain: Whatever smooths it — the load's own sluggishness or a deliberate RC low-pass filter — is really just attenuating those harmonics.

Major section

Start With the Decision

An LED or motor is an actuator, a device that acts on its surroundings; an audio input is a different kind of load.

PWM sends on-off pulses; a filter can smooth them.
Human perception: LED dimming (eye can't see >100 Hz flicker).
The eye cannot detect the flicker, and PWM saves scarce DAC outputs.

Major section

Applied: PWM vs DAC Output

The choice between PWM and DAC is a contract about duty-cycle resolution, frequency, filtering, settling time, and load sensitivity.

This page turns those ideas into a design contract: what the load actually sees, what timer settings cost, and what error matters most.
That observation connects duty-cycle arithmetic to the selection rule: PWM suits tolerant loads, while quiet bias and measurement signals need filtering or a true DAC.

PWM duty-cycle waveforms comparing 25 percent, 50 percent, and 75 percent on-time with average voltage examples for a 12 volt motor.

Major section

Applied: PWM vs DAC Output (continued)

For a visible LED, 12.9 mV-equivalent duty changes are usually fine.

Sets the on-fraction of each period.
What a slow load or filter actually sees.
An N -bit timer gives 2^N duty steps (256 steps for 8-bit).

Major section

Applied: PWM vs DAC Output (continued)

PWM is not a clean analog source.

Its spectrum is the DC average plus strong harmonics at the switching frequency and its multiples.
Whatever smooths it — the load's own sluggishness or a deliberate RC low-pass filter — is really just attenuating those harmonics.
Its output still takes time to settle and has finite accuracy.

Deck summary

Key takeaways

An LED or motor is an actuator, a device that acts on its surroundings; an audio input is a different kind of load.

The choice between PWM and DAC is a contract about duty-cycle resolution, frequency, filtering, settling time, and load sensitivity.
For a visible LED, 12.9 mV-equivalent duty changes are usually fine.
PWM is not a clean analog source.

Retrieval practice

Recall check 1 of 4

Voltage Vera says: answer from memory, then check your reasoning.

Q1A control load needs a low-noise, continuously varying voltage. Which output should the team test first?

AA true DAC with measured load drive and settling for the control voltage

BAn ADC as an output stage for the continuously varying load voltage

CRaw PWM pulses treated as a clean continuous voltage without filtering

DA GPIO held high as a fixed output for a varying voltage command

Show answer

Answer: A A DAC offers voltage steps without a PWM carrier; the load still needs proof.

Q2What maps a DAC input code fraction onto the reference voltage?

ADAC core

BDigital input

C5V reference

DAnalogue output (0-5V)

Show answer

Answer: A The DAC core maps the input code fraction onto the reference voltage.

Retrieval practice

Recall check 2 of 4

Voltage Vera says: answer from memory, then check your reasoning.

Q3A 3.3 V GPIO drives an LED through PWM at 25% duty cycle, and the LED responds only to the average. What average voltage does it effectively see?

AAbout 3.3 V because the pin reaches that high level during each cycle

BAbout 1.65 V by averaging the low and high levels at a 50% duty assumption

CAbout 0.825 V from 25% of the 3.3 V high level over each PWM cycle

DAbout 0 V because a pulsed output supposedly has no time average

Show answer

Answer: C A slow load sees the time-average, Vavg = D x Vsupply = 0.25 x 3.3 = 0.825 V.

Retrieval practice

Recall check 3 of 4

Voltage Vera says: answer from memory, then check your reasoning.

Q4On a counter-based timer with a fixed clock, you increase PWM resolution from 8-bit to 12-bit for smoother LED dimming. What happens to the PWM frequency, and why does it matter?

AIt stays fixed because timer resolution supposedly does not affect period.

BIt falls by 16× at fixed clock, which can move LED PWM into visible flicker.

CIt rises by 16× because more counter states shorten each PWM period.

DIt becomes irrelevant because LED flicker cannot depend on PWM rate.

Show answer

Answer: B More bits means more counts per period at the same clock, so fpwm = f_clk / 2^N drops (2^12 / 2^8 = 16x lower).

Retrieval practice

Recall check 4 of 4

Voltage Vera says: answer from memory, then check your reasoning.

Q5A PWM output through an RC low-pass filter still shows too much ripple. Without changing the average output voltage, which changes reduce the ripple?

AIncrease duty cycle to 90%, changing the required average output voltage

BLower PWM frequency so more switching harmonics pass through the filter

CRaise PWM frequency or increase R or C while preserving the set duty cycle

DRemove the low-pass filter and deliver unattenuated pulses to the load

Show answer

Answer: C Ripple falls as fpwm x R x C rises, so a higher switching frequency or a larger RC both help; the trade-off is that larger RC lengthens settling time.

Print reference

Answers 1 of 2

Answer key.

A · A DAC offers voltage steps without a PWM carrier; the load still needs proof.
A · The DAC core maps the input code fraction onto the reference voltage.
C · A slow load sees the time-average, Vavg = D x Vsupply = 0.25 x 3.3 = 0.825 V.
B · More bits means more counts per period at the same clock, so fpwm = f_clk / 2^N drops (2^12 / 2^8 = 16x lower).

Print reference

Answers 2 of 2

Answer key.

C · Ripple falls as fpwm x R x C rises, so a higher switching frequency or a larger RC both help; the trade-off is that larger RC lengthens settling time.